Since the advent of the integrated circuit the electronics system designer has employed a number of circuit architectures for realizing an eventual micro-miniaturized implementation of an original signal processing system. In the early days of integrated circuit development the semiconductor engineer performed what was essentially a manual translation of the original circuit design, so as to provide an architecture that was effectively a customized version of each of the circuits contained within the system. Because each chip architecture was specifically and principally manually tailored to map the circuit components of the system onto a wafer environment, the eventual production costs of the final realization of the system, in terms of man hours necessary to map, resulted in a price per unit that could be prohibitively expensive in the commercial marketplace for small volumes of parts. The cost of this mapping or translating activity (man-hours, schedule uncertainty, re-cycles due to multiple errors) could create an economic barrier to the electronic system designer's use of available technology.
In an attempt to insert a "standardization" factor into the design and manufacture of chip architectures, for the purpose of reducing design mapping or translation complexity and cost, user involvement design schemes were proposed. A first of these schemes, termed the gate array, employs a chip architecture that contains dedicated geographic areas on the chip within which are disposed either elemental circuit devices (transistors or gates) or interconnect highways, through the selective intercoupling of which an overall circuit design can be mapped into silicon. Typically, in a gate array architecture, some small percentage of the available area of the chip contains an array of logic gates (e.g. two-input NAND gates). Another portion (and larger region) of the chip is provided with wiring/interconnect channels through which selected ones of the gates may be interconnected to realize a desired multi-function logic circuit. Unlike the custom integrated circuit approach, discussed supra, in which the semiconductor designer is required to customize a chip architecture to map a given system's circuits, the gate array scheme places a limit on the freedom of design of the system engineer: all circuits of the system must obey ground rules governed by the types and availability of the gates and interconnects of the array layout. Because of the vast complexity that any particular instantiation of the eventual logic design may take, a substantial portion of the chip is reserved for interconnects for the gates, typically limiting the useful active area of the chip to ten percent or less. As a result, not only is circuit packing density reduced, but because of the substantial signal propagation interconnect path area, circuit speed is reduced, thereby adversely affecting system performance.
In an effort to improve upon both the active area availability and the limited resources with which the system designer had to work, chip architecture development evolved from the gate array approach into the use of "standard cells". In accordance with the standard cell technique, a prescribed library of types of restricted-function building blocks (e.g. inverters, up/down counters) are provided for design implementation. Using manual or automatic routing techniques, a system design of any magnitude can be mapped to silicon, subject to photolithographic and yield constraints. The resulting silicon version of the system resembles the gate array in structural appearance: comparatively small regions of active area separated by large areas of interconnections of the standard cells. Unlike the gate array approach wherein the system designer was confined to circuit-implement all system functions using a fixed quantity of very basic components (gates), the standard cell approach offers somewhat improved flexibility in that the level of circuit design has reached a slightly higher degree of sophistication, as the basic building blocks are not limited to only a single type, nor are they limited to a very rudimentary (e.g. gate or transistor) level. Still, like the gate array architecture, most of the chip (80%) is reserved for interconnects, so that the active area and, consequently circuit speed, remain undesirably limited. Moreover, the limited variety of available standard cells still forces the system designer to spend a considerable amount of time on an architectural implementation plane that is essentially a "don't care" exercise, and consequently, not cost effective. Specifically, in either the gate array or the standard cell methodology the system designer is forced to decompose his system level block diagram to the limited set of building blocks of low complexity.